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120 dB Range (3 nA to 3 mA) Dual Logarithmic Converter ADL5310
FEATURES
2 independent channels optimized for photodiode interfacing 6-decade input dynamic range Law conformance 0.3 dB from 3 nA to 3 mA Temperature-stable logarithmic outputs Nominal slope 10 mV/dB (200 mV/dec), externally scalable Intercepts may be independently set by external resistors User-configurable output buffer amplifiers Single- or dual-supply operation Space-efficient, 24-lead 4 mm x 4 mm LFCSP Low power: < 10 mA quiescent current
VSUM COMM
FUNCTIONAL BLOCK DIAGRAM
665k VREF VRDZ OUT1 VOUT1
IRF1 VBIAS
SCL1 6.69k I TEMPERATURE LOG COMPENSATION 14.2k IPD1 INP1 OUT2 0.5V 2.5V 80k 20k COMM REFERENCE GENERATOR VOUT2 BIN1
VNEG
451
LOG1
Gain and absorbance measurements Multichannel power monitoring General-purpose baseband log compression
IRF2 VBIAS
14.2k I TEMPERATURE LOG COMPENSATION 6.69k
SCL2 BIN2
VNEG
PRODUCT DESCRIPTION
The ADL53101 low cost, dual logarithmic amplifier converts input current over a wide dynamic range to a linear-in-dB output voltage. It is optimized to determine the optical power in wide-ranging optical communication system applications, including control circuitry for lasers, optical switches, attenuators, and amplifiers, as well as system monitoring. The device is equivalent to a dual AD8305 with enhanced dynamic range (120 dB). While the ADL5310 contains two independent signal channels with individually configurable transfer function constants (slope and intercept), internal bias circuitry is shared between channels for improved power consumption and channel matching. Dual converters in a single, compact LFCSP package yield space-efficient solutions for measuring gain or attenuation across optical elements. Only a single supply is required; optional dual-supply operation offers added flexibility. The ADL5310 employs an optimized translinear structure that use the accurate logarithmic relationship between a bipolar transistor's base emitter voltage and collector current, with appropriate scaling by precision currents to compensate for the inherent temperature dependence. Input and reference current pins sink current ranging from 3 nA to 3 mA (limited to 60 dB between input and reference) into a fixed voltage defined by the VSUM potential. The VSUM potential is internally set to 500 mV but may be externally grounded for dual-supply operation, and for additional applications requiring voltage inputs.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
IPD2 INP2 VSUM 665k VREF
451
LOG2
Figure 1.
The logarithmic slope is set to 10 mV/dB (200 mV/decade) nominal and can be modified using external resistors and the independent buffer amplifiers. The logarithmic intercepts for each channel are defined by the individual reference currents, which are set to 3 A nominal for maximum input range by connecting 665 k resistors between the 2.5 V VREF pins and the IRF1 and IRF2 inputs. Tying VRDZ to VREF effectively sets the x-intercept four decades below the reference current-- typically 300 pA for a 3 A reference. The use of individually optimized reference currents may be valuable when using the ADL5310 for gain or absorbance measurements where each channel input has a different currentrange requirement. The reference current inputs are also fully functional dynamic inputs, allowing log ratio operation with the reference input current as the denominator. The ADL5310 is specified for operation from -40C to +85C.
1
US Patents: 4,604,532, 5,519,308. Other patents pending.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
04415-0-001
COMM
4.99k
APPLICATIONS
4.99k
ADL5310 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 General Structure............................................................................ 11 Theory.......................................................................................... 11 Managing Intercept and Slope .................................................. 12 Response Time and Noise Considerations.............................. 12 Applications..................................................................................... 13 Calibration................................................................................... 14 Minimizing Crosstalk ................................................................ 14 Relative and Absolute Power Measurements .......................... 15 Characterization Methods......................................................... 16 Evaluation Board ............................................................................ 17 Outline Dimensions ....................................................................... 20 Ordering Guide........................................................................... 20
REVISION HISTORY
9/04--Data Sheet Changed from Rev. 0 to Rev. A Changes to Ordering Guide .......................................................... 20 11/03--Revision 0: Initial Version
Rev. A | Page 2 of 20
ADL5310 SPECIFICATIONS
VP = 5 V, VN = 0 V, TA = 25C, RREF = 665 k, and VRDZ connected to VREF, unless otherwise noted. Table 1.
Parameter INPUT INTERFACE Specified Current Range, IPD Input Current Min/Max Limits Reference Current, IREF, Range Summing Node Voltage Temperature Drift Input Offset Voltage LOGARITHMIC OUTPUTS Logarithmic Slope Logarithmic Intercept1 Law Conformance Error Wideband Noise2 Small Signal Bandwidth Maximum Output Voltage Minimum Output Voltage Output Resistance REFERENCE OUTPUT Voltage wrt Ground
2
Conditions Pins 1 to 6: INP1 and INP2, IRF1 and IRF2, VSUM Flows toward INP1 pin or INP2 pin Flows toward INP1 pin or INP2 pin Flows toward IRF1 pin or IRF2 pin Internally preset; user alterable -40C < TA < +85C VIN - VSUM, VIREF - VSUM Pin 15 and Pin 16: LOG1 and LOG2 -40C < TA < +85C -40C < TA < +85C 10 nA < IPD < 1 mA 3 nA < IPD < 3 mA IPD > 3 A; output referred IPD = 3 A Limited by VN = 0 V
Min 3n 3n 0.46 -20 190 185 165 40
Typ
Max 3m 10 m 3m 0.54 +20
Unit A A A V mV/C mV mV/dec mV/dec pA pA dB dB V/Hz MHz V V k V V mA
0.5 0.030
200 300 0.1 0.3 0.5 1.5 1.7 0.10 5 2.5 20 4
210 215 535 1940 0.4 0.6
4.375 Pin 7 and Pin 24 (internally shorted): VREF -40C < TA < +85C Sourcing (grounded load) Load current < 10 mA Pins 12 to 14 and 17 to 19: OUT2, SCL2, BIN2, BIN1, SCL1, and OUT1 Flowing out of Pins 13, 14, 17, and 18 Load current < 10 mA; gain = 1 RL = 1 k to ground RL = 1 k to ground Gain = 1 0.2 V to 4.8 V output swing Pins 8 and 9: VPOS; Pins 10, 11, and 20: VNEG (VP - VN ) 12 V Input currents < 10 A (VP - VN ) 12 V 2.45 2.42
5.625 2.55 2.58
Maximum Output Current Incremental Output Resistance OUTPUT BUFFERS Input Offset Voltage Input Bias Current Incremental Input Resistance Incremental Output Resistance Output High Voltage Output Low Voltage Peak Source/Sink Current Small-Signal Bandwidth Slew Rate POWER SUPPLY Positive Supply Voltage Quiescent Current Negative Supply Voltage (Optional)
-20 0.4 35 0.5 VP - 0.1 0.10 30 15 15 3 -5.5 5 9.5 0
+20
mV A M V V mA MHz V/s
12 11.5
V mA V
1 2
Other values of logarithmic intercept can be achieved by adjustment of RREF. Output noise and incremental bandwidth are functions of input current; measured using output buffer connected for GAIN = 1.
Rev. A | Page 3 of 20
ADL5310 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Supply Voltage VP - VN Input Current Internal Power Dissipation JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering 60 sec) Rating 12 V 20 mA 500 mW 35C/W1 125C -40C to +85C -65C to +150C 300C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
1
With paddle soldered down.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 4 of 20
ADL5310 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMM COMM VNEG
20
VRDZ
VREF
24
23
22
21
19
OUT1
VSUM 1 INP1
2
PIN 1 INDICATOR
18 17
SCL1 BIN1 LOG1 LOG2 BIN2 SCL2
IRF1 3 IRF2 4 INP2 5 VSUM 6
ADL5310
DUAL LOG AMP TOP VIEW (Not to Scale)
16 15 14 13
VPOS
VPOS
VREF
VNEG
VNEG
Figure 2. 24-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No. 1, 6 2 3 4 5 7, 24 8, 9 10, 11, 20 12 13 14 15 16 17 18 19 21, 22 23 Mnemonic VSUM INP1 IRF1 IRF2 INP2 VREF VPOS VNEG OUT2 SCL2 BIN2 LOG2 LOG1 BIN1 SCL1 OUT1 COMM VRDZ Function Guard Pin. Used to shield the INP1 and INP2 input current lines, and for optional adjustment of the input summing node potentials. Pin 1 and Pin 6 are internally shorted. Channel 1 Numerator Input. Accepts (sinks) photodiode current IPD1. Usually connected to photodiode anode such that photocurrent flows into INP1. Channel 1 Denominator Input. Accepts (sinks) reference current, IRF1. Channel 2 Denominator Input. Accepts (sinks) reference current, IRF2. Channel 2 Numerator Input. Accepts (sinks) photodiode current IPD2. Usually connected to photodiode anode such that photocurrent flows into INP2. Reference Output Voltage of 2.5 V. Pin 7 and Pin 24 are internally shorted. Positive Supply, (VP - VN) 12 V. Both pins must be connected externally. Optional Negative Supply, VN. These pins are usually grounded. For more details, see the General Structure and Applications sections. All VNEG pins must be connected externally. Buffer Output for Channel 2. Buffer Amplifier Inverting Input for Channel 2. Buffer Amplifier Noninverting Input for Channel 2. Output of the Logarithmic Front End for Channel 2. Output of the Logarithmic Front End for Channel 1. Buffer Amplifier Noninverting Input for Channel 1. Buffer Amplifier Inverting Input for Channel 1. Buffer Output for Channel 1. Analog Ground. Pin 21 and Pin 22 are internally shorted. Intercept Shift Reference Input. The top of a resistive divider network that offsets VLOG to position the intercept. Normally connected to VREF; may also be connected to ground when bipolar outputs are to be provided.
Rev. A | Page 5 of 20
OUT2
04415-0-002
7
8
9
10
11
12
ADL5310 TYPICAL PERFORMANCE CHARACTERISTICS
VP = 5 V, VN = 0 V, RREF = 665 k, TA = 25C, unless otherwise noted.
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2
04415-0-003
TA = -40C, 0C, +25C, +70C, +85C VIN = 0V
2.0 1.5 1.0 +25C 0.5 0 -0.5 0C -1.0 -1.5
04415-0-006 04415-0-007 04415-0-008
ERROR (dB (10mV/dB))
+85C +70C
VLOG (V)
-40C
0 1n
10n
100n
1
10
100
1m
10m
-2.0 1n
10n
100n
1
10
100
1m
10m
IINP (A)
IINP (A)
Figure 3. VLOG vs. IINP for Multiple Temperatures
1.8 1.6 1.4
Figure 6. Law Conformance Error vs. IINP for Multiple Temperatures, Normalized to 25C
2.0 1.5 1.0 +70C 0.5 0 -0.5 -1.0 -1.5
04415-0-004
TA = -40C, 0C, +25C, +70C, +85C VIN = 0V
ERROR (dB (10mV/dB))
1.2
+85C +25C
VLOG (V)
1.0 0.8 0.6 0.4 0.2 0 1n 10n 100n 1 10 100 1m 10m IREF (A)
-40C
0C
-2.0 1n
10n
100n
1
10
100
1m
10m
IREF (A)
Figure 4. VLOG vs. IREF for Multiple Temperatures (IINP = 3 A)
1.8 1.6 1.4 300nA 1.2 30nA 3nA 3A
Figure 7. Law Conformance Error vs. IREF for Multiple Temperatures, Normalized to 25C (IINP = 3 A)
1.0 0.8 3mA 0.6
ERROR (dB (10mV/dB))
300A 30A 3A
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
VLOG (V)
1.0 0.8 0.6
300nA
3mA 300A
0.4 0.2
30A
3nA
30nA
1n
10n
100n
1
10
100
1m
10m
04415-0-005
0 IINP (A)
-1.0 1n
10n
100n
1
10
100
1m
10m
IINP (A)
Figure 5. VLOG vs. IINP for Multiple Values of IREF, Decade Steps from 3 nA to 3 mA
Rev. A | Page 6 of 20
Figure 8. Law Conformance Error vs. IINP for Multiple Values of IREF, Decade Steps from 3 nA to 3 mA
ADL5310
1.8 1.6 1.4 1.2
VLOG (V)
1.0 0.8 0.6 3nA 30nA 300nA 3A 0.2 0 -0.2 -0.4 300A -0.6 30A -0.8
04415-0-009
30A 300A
ERROR (dB (10mV/dB))
0.4 3A
1.0 0.8 3nA 0.6 0.4 0.2 0 1n 10n 100n 1 10 100 30nA 300nA 3A
3mA
3mA 3mA
1m
10m
10n
100n
1
10
100
1m
10m
IREF (A)
IREF (A)
Figure 9. VLOG vs. IREF for Multiple Values of IINP, Decade Steps from 3 nA to 3 mA
Figure 12. Law Conformance Error vs. IREF for Multiple Values of IINP, Decade Steps from 3 nA to 3 mA
1.0 0.8 +5V, 0V 0.6 +12V, 0V
2.0 TA = 25C 1.5 +12V, 0V +9V, 0V +3V, 0V 1.0 0.5 0 -0.5 -1.0 MEAN - 3 MEAN + 3
ERROR (dB (10mV/dB))
0.4 0.2 0 -0.2 -0.4 -0.6 -0.8
+5V, -5V
+5V, -5V
ERROR (dB (10mV/dB))
-1.5
04415-0-010 04415-0-013 04415-0-014
-1.0 1n
10n
100n
1
10
100
1m
10m
-2.0 1n
10n
100n
1
10
100
1m
10m
IINP (A)
IPD (A)
Figure 10. Law Conformance Error vs. IINP for Various Supply Conditions
Figure 13. Law Conformance Error Distribution (3 to Either Side of Mean)
2.0 TA = 0C, 70C 1.5 1.0 0.5 0 -0.5 -1.0 -1.5
04415-0-011
4 TA = -40C, 85C 3 MEAN + 3 AT -40C MEAN + 3 AT 70C 2 1 0 -1 -2 -3 -4 1n MEAN - 3 AT -40C MEAN + 3 AT +85C
ERROR (dB (10mV/dB))
MEAN 3 AT 0C
MEAN - 3 AT 70C
-2.0 1n
10n
100n
1
10
100
1m
10m
ERROR (dB (10mV/dB))
10n
100n
1
10
100
1m
10m
IPD (A)
IPD (A)
Figure 11. Law Conformance Error Distribution (3 to Either Side of Mean)
Figure 14. Law Conformance Error Distribution (3 to Either Side of Mean)
Rev. A | Page 7 of 20
04415-0-012
-1.0 1n
ADL5310
15 10 5 3nA 30A 30nA 300nA
1.4 T-RISE < 1s T-FALL < 1s 1.2 T-RISE < 1s T-FALL < 1s 30A TO 300A 3A TO 30A 300nA TO 3A 30nA TO 300nA 1.0 T-RISE < 1s T-FALL < 5s 0.8 T-RISE < 5s T-FALL < 10s 0.6 T-RISE < 10s T-FALL < 40s 0.4 0.2
04415-0-015
1.6
NORMALIZED RESPONSE (dB)
0 -5
300A TO 3mA
-15 -20 -25 -30 -35 -40 -45 1k 10k 100k 1M 10M 3mA 3A
300A
VOUT (V)
-10
T-RISE < 30s T-FALL < 80s
3nA TO 30nA
100M
0
20
40
60
80
100
120
140
160
180
200
FREQUENCY (Hz)
TIME (s)
Figure 15. Small Signal AC Response, IINP to VOUT (AV = 1) (5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
15 10 5 30nA 300nA 3mA
1.4 1.6
Figure 18. Pulse Response--IINP to VOUT (AV = 1) in Consecutive 1-Decade Steps
NORMALIZED RESPONSE (dB)
0 -5 -10 -15 -20 -25 -30 -35 -40 -45
04415-0-016
T-RISE < 80s T-FALL < 30s 1.2 T-RISE < 40s T-FALL < 10s
3nA TO 30nA 30nA TO 300nA 300nA TO 3A 3A TO 30A 30A TO 300A 300A TO 3mA
3nA
300A
VOUT (V)
1.0 T-RISE < 10s T-FALL < 5s 0.8 T-RISE < 1s T-FALL < 1s 0.6 T-RISE < 1s T-FALL < 1s 0.4 T-RISE < 1s T-FALL < 1s 0.2
04415-0-019 04415-0-020
3A
30A
-50 100
0 0 20 40 60 80 100 120 140 160 180 200 TIME (s)
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 16. Small Signal AC Response, IREF to VOUT (AV = 1) (5% Sine Modulation, Decade Steps from 3 nA to 3 mA)
100
5.0
Figure 19. Pulse Response--IREF to VOUT (AV = 1) in Consecutive 1-Decade Steps
3nA 10 30nA
V rms/ Hz
4.0
3.0
1 300nA 3A
mV rms
2.0
0.1
1.0
300A 0.01 100
3mA
30A
1k
10k
100k
1M
10M
04415-0-017
0 1n
10n
100n
1
10
100
1m
10m
FREQUENCY (Hz)
IINP (A)
Figure 17. Spot Noise Spectral Density at VOUT vs. Frequency (AV = 1) for IINP in Decade Steps from 3 nA to 3 mA
Figure 20. Total Wideband Noise Voltage at VOUT vs. IINP (AV = 1)
Rev. A | Page 8 of 20
04415-0-018
-50 100
0
ADL5310
25 20 15 10 MEAN + 3 5 0 -5 MEAN - 3 -10 -15 -20
04415-0-021
5 4 3 2
VINPT DRIFT (mV)
VREF DRIFT (mV)
1 0 -1 -2 -3 -4 -5
MEAN + 3
MEAN - 3
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 21. VREF Drift vs. Temperature (3 to Either Side of Mean) Normalized to 25C
6 5 4 3
Figure 24. VINPT Drift vs. Temperature (3 to Either Side of Mean) Normalized to 25C
7 6 5 4
VY DRIFT (mV/dec)
2 1 0 -1 -2 -3 -4 -5
MEAN + 3
VY DRIFT (mV/dec)
3 2 1 0 -1 -2 -3 -4 -5 MEAN - 3 MEAN + 3
MEAN - 3
04415-0-022
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 22. Slope Drift vs. Temperature (3 to Either Side of Mean) Normalized to 25C
200 200 150 100 MEAN + 3 50 50 0 -50 -100 -150
04415-0-023
Figure 25. Slope Mismatch Drift vs. Temperature (VY1 - VY2, 3 to Either Side of Mean) Normalized to 25C
150
100
IZ DRIFT (pA)
0 MEAN - 3
IZ DRIFT (pA)
MEAN + 3
MEAN - 3
-50
-100 -150 -40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
TEMPERATURE (C)
TEMPERATURE (C)
Figure 23. Intercept Drift vs. Temperature (3 to Either Side of Mean) Normalized to 25C
Figure 26. Intercept Mismatch Drift vs. Temperature (IZ1 - IZ2, 3 to Either Side of Mean) Normalized to 25C
Rev. A | Page 9 of 20
04415-0-026
-200 -40 -30 -20 -10
04415-0-025
-6 -40 -30 -20 -10
-6 -40 -30 -20 -10
04415-0-024
-25 -40 -30 -20 -10
-6 -40 -30 -20 -10
ADL5310
700 450 400 350 500 300
COUNT COUNT
04415-0-027
600
400 300
250 200 150
200 100 100 50
04415-0-030 04415-0-032 04415-0-031
0 190
0 -9 -6 -3 0 3 6 9 SLOPE MISMATCH (mV/dec)
195
200 SLOPE (mV/dec)
205
210
Figure 27. Distribution of Logarithmic Slope
Figure 30. Distribution of Channel-to-Channel Slope Mismatch (VY1 - VY2)
600
500
500
400
400
COUNT COUNT
04415-0-028
300
300
200 200 100 100
0 100
200
300 INTERCEPT (pA)
400
500
0 -300
-200
-100
0
100
200
300
INTERCEPT MISMATCH (pA)
Figure 28. Distribution of Logarithmic Intercept
Figure 31. Distribution of Channel-to-Channel Intercept Mismatch (IZ1 - IZ2)
700
500
600 400 500
COUNT
04415-0-029
300
COUNT
400 300
200
200 100 100 0 -9 -6 -3 0 3 6 9 VINPT - VSUM VOLTAGE (mV)
0 2.46
2.48
2.50 VREF VOLTAGE (V)
2.52
2.54
Figure 29. Distribution of VREF (RL = 100 k)
Figure 32. Distribution of Offset Voltage (VINPT - VSUM)
Rev. A | Page 10 of 20
ADL5310 GENERAL STRUCTURE
The ADL5310 addresses a wide variety of interfacing conditions to meet the needs of fiber optic supervisory systems and is useful in many nonoptical applications. These notes explain the structure of this unique style of translinear log amp. Figure 33 shows the key elements of one of the two identical on-board log amps.
BIAS GENERATOR PHOTODIODE 2.5V INPUT CURRENT 80k IPD INP1 (INP2) 0.5V VSUM IREF VREF IREF 20k COMM 0.5V 14.2k VRDZ 0.5V Q1 VBE1 Q2 VBE2 6.69k COMM
04415-0-033
THEORY
The base-emitter voltage of a bipolar junction transistor (BJT) can be expressed by Equation 1, which immediately shows its basic logarithmic nature: VBE = kT/q ln(IC/IS) (1) where: IC is the collector current. IS is a scaling current, typically only 10-17 A. kT/q is the thermal voltage, proportional to absolute temperature (PTAT), and is 25.85 mV at 300 K. IS is never precisely defined and exhibits an even stronger temperature dependence, varying by a factor of roughly a billion between -35C and +85C. Thus, to make use of the BJT as an accurate logarithmic element, both of these temperature dependencies must be eliminated. The difference between the base-emitter voltages of a matched pair of BJTs, one operating at the photodiode current IPD and the other operating at a reference current IREF, can be written as VBE1 - VBE2 = kT/q ln(IPD/IS) - kT/q ln(IREF/IS) = ln(10) kT/q log10(IPD/IREF) = 59.5 mV log10(IPD/IREF) (T = 300 K) The uncertain, temperature-dependent saturation current, IS, that appears in Equation 1 has therefore been eliminated. To eliminate the temperature variation of kT/q, this difference voltage is processed by what is essentially an analog divider. Effectively, it puts a variable under Equation 2. The output of this process, which also involves a conversion from voltage mode to current mode, is an intermediate, temperaturecorrected current: ILOG = IY log10(IPD/IREF) (3) where IY is an accurate, temperature-stable scaling current that determines the slope of the function (change in current per decade). For the ADL5310, IY is 44 A, resulting in a temperature-independent slope of 44 A/decade for all values of IPD and IREF. This current is subsequently converted back to a voltage-mode output, VLOG, scaled 200 mV/decade. It is apparent that this output should be 0 for IPD = IREF and would need to swing negative for smaller values of input current. To avoid this, IREF would need to be as small as the smallest value of IPD. Accordingly, an offset voltage is added to VLOG to shift it upward by 0.8 V when VRDZ is directly connected to VREF. This moves the intercept to the left by four decades (at 200 mV/decade), from 3 A to 300 pA: ILOG = IY log10(IPD/IINTC) (4) where IINTC is the operational value of the intercept current. Because values of IPD < IINTC result in a negative VLOG, a negative supply of sufficient value is required to accommodate this situation. (2)
VBE1 VBE2
TEMPERATURE COMPENSATION (SUBTRACT AND DIVIDE BY TK) 44A/dec 451 VLOG
VNEG (NORMALLY GROUNDED)
Figure 33. Simplified Schematic of Single Log Amp
The photodiode current IPD is received at either Pin INP1 or Pin INP2. The voltages at these nodes are approximately equal to the voltage on the adjacent guard pins, VSUM, as well as reference inputs IRF1 and IRF2, due to the low offset voltage of the JFET operational amplifiers. Transistor Q1 converts IPD to a corresponding logarithmic voltage, as shown in Equation 1. A finite positive value of VSUM is needed to bias the collector of Q1 for the usual case of a single-supply voltage. This is internally set to 0.5 V, one-fifth of the 2.5 V reference voltage that appears on Pin VREF. Both VREF pins are internally shorted, as are both VSUM pins. The resistance at the VSUM pin is nominally 16 k; this voltage is not intended as a general bias source. The ADL5310 also supports the use of an optional negative supply voltage, VN, at Pin VNEG. When VN is 0.5 V or more negative, VSUM may be connected to ground; thus, INP1, INP2, IRF1, and IRF2 assume this potential. This allows operation as a voltage-input logarithmic converter by the inclusion of a series resistor at either or both inputs. Note that the resistor setting IREF for each channel needs to be adjusted to maintain the intercept value. Also note that the collector-emitter voltages of Q1 and Q2 are the full VN and effects due to self-heating cause errors at large input currents. The input-dependent VBE1 of Q1 is compared with the reference VBE2 of a second transistor, Q2, operating at IREF. IREF is generated externally to a recommended value of 3 A. However, other values over a several-decade range can be used with a slight degradation in law conformance.
Rev. A | Page 11 of 20
ADL5310
The voltage VLOG is generated by applying ILOG to an internal resistance of 4.55 k, formed by the parallel combination of a 6.69 k resistor to ground and a 14.2 k resistor to Pin VRDZ (typically tied to the 2.5 V reference, VREF). At the LOG1 (LOG2) pin, the output current ILOG generates a voltage of VLOG = ILOG x 4.55 k = 44 A x 4.55 k x log10(IPD/IINTC) = VY log10(IPD/IINTC) (5) Thus, the effective intercept current IINTC is only one tenthousandth of IREF, corresponding to 300 pA when using the recommended value of IREF = 3 A. The slope can be reduced by attaching a resistor between the log amp output pin, LOG1 or LOG2, and ground. This is strongly discouraged given that the on-chip resistors do not ratio correctly to the added resistance. Also, it is rare that one would wish to lower the basic slope of 10 mV/dB; if this is needed, it should be effected at the low impedance output of the buffer amps, which are provided to avoid such miscalibration and to allow higher slopes to be used. Each of the ADL5310's buffers is essentially an uncommitted operational amplifier with rail-to-rail output swing, good loaddriving capabilities, and a typical unity-gain bandwidth of 15 MHz. In addition to allowing the introduction of gain, using standard feedback networks and thereby increasing the slope voltage VY, the buffer can be used to implement multipole, lowpass filters, threshold detectors, and a variety of other functions. Further details on these applications can be found in the AD8304 data sheet.
where VY = 200 mV/decade or 10 mV/dB. Note that any resistive loading on LOG1 (LOG2) lowers this slope and results in an overall scaling uncertainty. This is due to the variability of the on-chip resistors compared to the off-chip load. As a consequence, this practice is not recommended. VLOG may also swing below ground when dual supplies (VP and VN) are used. When VN = -0.5 V or larger, the input Pins INP1 (INP2) and IRF1 (INP2) may be positioned at ground level simply by grounding VSUM. Care must be taken to limit the power consumed by the input BJT devices when using a larger negative supply, because self-heating degrades the accuracy at higher currents.
MANAGING INTERCEPT AND SLOPE
When using a single supply, VRDZ should be directly connected to VREF to allow operation over the entire 6-decade input current range. As noted in the Theory section, this introduces an accurate offset voltage of 0.8 V at the LOG1 and LOG2 pins, equivalent to four decades, resulting in a logarithmic transfer function that can be written as VLOG = VY log10(104 x IPD/IREF) = VY log10(IPD/IINTC) where IINTC = IREF/104. (6)
RESPONSE TIME AND NOISE CONSIDERATIONS
The response time and output noise of the ADL5310 are fundamentally a function of the signal current, IPD. For small currents, the bandwidth is proportional to IPD, as shown in Figure 15. The output low frequency voltage-noise spectral-density is a function of IPD (see Figure 17) and also increases for small values of IREF. Details of the noise and bandwidth performance of translinear log amps can be found in the AD8304 data sheet.
Rev. A | Page 12 of 20
ADL5310 APPLICATIONS
665k VSUM VREF VRDZ 5V VPOS COMM IRF1 IRF1 SCL1 2k 4.7nF VBIAS VNEG 6.69k I TEMPERATURE LOG COMPENSATION 14.2k IPD1 INP1 1k 1nF 20k COMM IRF2 2k 4.7nF VBIAS IRF2 6.69k IPD2 1k 1nF 1nF 665k INP2 VSUM COMM
04415-0-034
OUT1
IPD1 0.5log10 1nA
(
)
VOUT1 12k
8k
BIN1 LOG1 451 CFLT1 10 nF
OUT2 0.5V 80k 2.5V REFERENCE GENERATOR
IPD2 0.5log10 1nA
(
)
VOUT2 12k SCL2
8k
14.2k I TEMPERATURE LOG COMPENSATION
BIN2 LOG2 451 CFLT2 10 nF
VNEG
VREF
VNEG
COMM
Figure 34. Basic Connections for Fixed Intercept Use
The ADL5310 is easy to use in optical supervisory systems and in similar situations where a wide-ranging current is to be converted to its logarithmic equivalent--that is, represented in decibel terms. Basic connections for measuring a single current at each input are shown in Figure 34, which also includes various nonessential components, as explained next. The 2 V difference in voltage between the VREF and Input Pins INP1 and INP2, in conjunction with the external 665 k resistors RRF1 and RRF2, provides 3 A reference currents IRF1 and IRF2 into Pins IRF1 and IRF2. Connecting VRDZ to VREF raises the voltage at LOG1 and LOG2 by 0.8 V, effectively lowering each intercept current IINTC by a factor of 104 to position it at 300 pA. A wide range of other values for IREF, from 3 nA to 3 mA, may be used. The effect of such changes is shown in Figure 5 and Figure 8. Any temperature variation in RRF1 (RRF2) must be taken into account when estimating the stability of the intercept. Also, the overall noise increases when using very low values of IRF1 (IRF2). In fixed-intercept applications there is little benefit in using a large reference current, because doing so only compresses the low-current-end of the dynamic range when operated from a single supply. The capacitor between VSUM and ground is
strongly recommended to minimize the noise on this node, to reduce channel-to-channel crosstalk, and to help provide clean reference currents. In addition, each input and reference pin (INP1, INP2, IRF1, and IRF2) has a compensation network made up of a series resistor and capacitor. The junction capacitance of the photodiode along with the network capacitance of the board artwork around the input system creates a pole that varies widely with input current. The RC network stabilizes the system by simultaneously reducing this pole frequency and inserting a zero to compensate an additional pole inherent in the input system. In general, the 1 nF, 1 k network handles almost any photodiode interface. In situations where larger active area photodiodes are used, or when long input traces are used, the capacitor value may need to be increased to ensure stability. Although the signal and reference input systems are similar, additional care is required to ensure stable operation of the reference inputs at temperature extremes across the full current range of IRF1 (IRF2). It is recommended that filter components of 4.7 nF and 2 k should be used from Pin IRF1 (IRF2) to ground. Temperaturestable components should always be used in critical locations such as the compensation networks; Y5V-type chip capacitors are to be avoided due to their poor temperature stability.
Rev. A | Page 13 of 20
ADL5310
The optional capacitor from LOG1 (LOG2) to ground forms a single-pole, low-pass filter in combination with the 5 k resistance at this pin. For example, when using a CFLT of 10 nF, the 3 dB corner frequency is 3.2 kHz. Such filtering is useful in minimizing the output noise, particularly when IPD is small. Multipole filters are more effective in reducing the total noise; examples are provided in the AD8304 data sheet. Because the basic scaling at LOG1 (LOG2) is 0.2 V/decade, and thus a 4 V swing at the buffer output would correspond to 20 decades, it is often useful to raise the slope to make better use of the rail-to-rail voltage range. For illustrative purposes, both channels in Figure 34 provide a 0.5 V/decade overall slope (25 mV/dB). Thus, using IREF = 3 A, VLOG runs from 0.2 V at IPD = 3 nA to 1.4 V at IPD = 3 mA; the buffer output runs from 0.5 V to 3.5 V, corresponding to a dynamic range of 120 dB (electrical, that is, 60 dB optical power). Further information on adjusting the slope and intercept, using a negative supply, and additional operations can be found in the AD8305 data sheet. Figure 35 shows the improvement in accuracy when using a 2point calibration method. To perform this calibration, apply two known currents, I1 and I2, in the linear operating range between 10 nA and 1 mA. Measure the resulting output, V1 and V2, respectively, and calculate the slope m and the intercept b: m = (V1 - V2)/[log10(I1) - log10(I2)] b = V1 - m x log10(I1) The same calibration could be performed with two known optical powers, P1 and P2. This allows for calibration of the entire measurement system while providing a simplified relationship between the incident optical power and VLOG voltage: m = (V1 - V2)/(P1 - P2) b = V1 - m x P1 (9) (10) (7) (8)
CALIBRATION
Each channel of the ADL5310 has a nominal slope and intercept at LOG1 (LOG2) of 200 mV/decade and 300 pA, respectively, when configured as shown in Figure 34. These values are untrimmed and the slope alone may vary by as much as 7.5% over temperature. For this reason, it is recommended that a simple calibration be done to achieve increased accuracy. While the ADL5310 offers improved slope and intercept matching compared to a randomly selected pair of AD8305 log amps, the specified accuracy can only be achieved by calibrating each channel individually.
1.4 4
The uncalibrated error line in Figure 35 was generated assuming that the slope of the measured output was 200 mV/decade when in fact it was actually 194 mV/decade. Correcting for this discrepancy decreased measurement error up to 3 dB.
MINIMIZING CROSSTALK
Combining two high-dynamic-range logarithmic converters in one IC carries potential pitfalls concerning channel-to-channel isolation. Special care must be taken in several areas to ensure acceptable crosstalk performance, particularly when one or both channels may operate at very low input currents. Fastidious supply bypassing--also necessary for overall stability--and careful board layout are important first steps for minimizing crosstalk. While the shared bias circuitry improves channel-to-channel matching and reduces power consumption, it is also a source of crosstalk that must be mitigated. The VSUM pins, which are internally shorted, should be bypassed with at least 1 nF to ground, and 20 nF is recommended for operation at the lowest currents (<30 nA). VSUM is of particular importance because it acts as a reference voltage input for each input system, but without the bandwidth limitation at low currents that the primary inputs incur. Disturbances at the VSUM pin that are well within the bandwidth of the input are tracked by the loop and do not generate disturbances at the output (aside from the generally minor perturbation in reference currents caused by voltage variations at IRF1 and IRF2). For this reason, the pole frequency at VSUM, which has a 16 k typical source resistance, should be set below the minimum input system bandwidth for the lowest input current to be encountered. Because the low frequency noise at VSUM is also tracked by the loop within its available bandwidth, this is also a criterion for reducing the noise contribution at the output from the thermal noise of the 16 k source resistance at VSUM.
1.2
UNCALIBRATED ERROR
3
VLOG (V)
0.8
MEASURED OUTPUT
1
0.6 CALIBRATED ERROR
0
0.4
-1
0.2
IDEAL OUTPUT
-2
04415-0-035
0 1n
10n
100n
1
10
100
1m
-3 10m
IPD (A)
Figure 35. Using 2-Point Calibration to Increase Measurement Accuracy
Rev. A | Page 14 of 20
ERROR (dB (10mV/dB))
1.0
2
ADL5310
A 10 nF capacitor on each VSUM pin (20 nF parallel equivalent) combined with the 16 k source resistance yields a 500 Hz pole, which is sufficiently below the bandwidth for the minimum input current of 3 nA. Residual crosstalk disturbance is particularly problematic at the lowest currents for two reasons. First, the loop is unable to reject summing node disturbances beyond the limited bandwidth. Second, the settling response at the lowest currents to any residual disturbance is significantly slower than that for input currents even one or two decades higher (see Figure 18).
12 ACTIVE CHANNEL OUTPUT PULSE, 1-DECADE STEP 3A TO 30A
INACTIVE CHANNEL OUTPUT (mV)
relative gain or absorbance measurement. A more straightforward analog implementation includes the use of a current mirror, as shown in Figure 37. The current mirror is used to feed an opposite polarity replica of the cathode photocurrent of PD2 into Channel 2 of the ADL5310. This allows one channel to be used as an absolute power meter for the optical signal incident on PD2, while the opposite channel is used to directly compute the log ratio of the two input signals.
5V 0.1F VSUM 1nF 5V VPOS OUT2 2*
ADL5310
COMM
1.2
IIN2 *2(V) 0.2log10 100pA
(
)
SCL2 BIN2
9
1.0
ACTIVE CHANNEL OUTPUT (V)
IIN2=IPD2 1k 4.7nF INP2
log
6 IINP - 3nA 3 IINP - 10nA IINP - 100nA
0.8
I TEMPERATURE LOG2 COMPENSATION
LOG2 1nF
0.6
0 IINP - 30nA -3 INACTIVE CHANNEL RESPONSE
0.4
2M 1k 4.7nF
IRF2 VRDZ VREF
log 21**
OUT1 BIAS GENERATOR IIN1 **21(V) 0.2log10 I PD2
0.2
0
0.5
1.0
1.5
2.0
04415-0-036
-6 TIME (ms)
0 2.5
(
)
SCL1 BIN1
IPD2 PD2 InGaAs PIN 1k 4.7nF 5V
IRF1
log
Figure 36. Crosstalk Pulse Response for Various Input Current Values
I TEMPERATURE LOG1 COMPENSATION
LOG1 1nF
Figure 36 shows the measured response of an inactive channel (dc input) to a 1-decade current step on the input of the active channel for several inactive channel dc current values. Additional system considerations may be necessary to ensure adequate settling time following a known transient when one or both channels are operating at very low input currents.
PD1 InGaAs PIN IIN1 1k 0.1F INP1
log COMM
04415-0-037
4.7nF VSUM 1nF
VNEG
COMM
RELATIVE AND ABSOLUTE POWER MEASUREMENTS
When properly calibrated, the ADL5310 provides two independent channels capable of accurate absolute optical power measurements. Often, it is desirable to measure the relative gain or absorbance across an optical network element, such as an optical amplifier or variable attenuator. If each channel has identical logarithmic slopes and intercepts, this can easily be done by differencing the output signals of each channel. In reality, channel mismatch can result in significant errors over a wide range of input levels if left uncompensated. Postprocessing of the signal can be used to account for individual channel characteristics. This requires a simple calculation of the expected input level for a measured log voltage, followed by differencing of the two signal levels in the digital domain for a
Figure 37. Absolute and Relative Power Measurement Application Using Modified Wilson Current Mirror
The presented current mirror is a modified Wilson mirror. Other current mirror implementations would also work, though the modified Wilson mirror provides fairly constant performance over temperature. It is essential to use matched pair transistors when designing the current mirror to minimize the effects of temperature gradients and beta mismatch.
Rev. A | Page 15 of 20
ADL5310
The solution in Figure 37 is no longer subject to potential channel mismatch issues. Individual channel slope and intercept characteristics can be calibrated independently. The accuracy was verified using a pair of calibrated current sources. The performance of the circuit depicted in Figure 37 is shown in Figure 38 and Figure 39. Multiple transfer functions and error plots are provided for various power levels. The accuracy is better than 0.1 dB over a 5-decade range. The dynamic range is slightly reduced for strong IIN input currents. This is due to the limited available swing of the VLOG pin and can be recovered through careful selection of input and output optical tap coupling ratios.
1.8 1.6 1.4
OUTPUT VOLTAGE (V)
CHARACTERIZATION METHODS
During the characterization of the ADL5310, the device was treated as a precision current-input logarithmic converter, because it is impractical to generate accurate photocurrents by illuminating a photodiode. The test currents were generated by using either a well-calibrated current source, such as the Keithley 236, or a high value resistor from a voltage source to the input pin. Great care is needed when using very small input currents. For example, the triax output connection from the current generator was used with the guard tied to VSUM. The input trace on the PC board was guarded by connecting adjacent traces to VSUM. These measures are needed to minimize the risk of leakage current paths. With 0.5 V as the nominal bias on the INP1 (INP2) pin, a leakage-path resistance of 1 G to ground would subtract 0.5 nA from the input, which amounts to a -1.6 dB error for a 3 nA source current. Additionally, the very high sensitivity at the input pins and the long cables commonly needed during characterization allow 60 Hz and RF emissions to introduce substantial measurement errors. Careful guarding techniques are essential to reducing the pickup of these spurious signals.
2 WHEN IPD1 = 100A
1.2 1.0 0.8 0.6 0.4 0.2 0 -20
04415-0-038
21 FOR MULTIPLE VALUES OF IPD1
-10
0
10
20
30
40
50
60
Additional information, including test setups, can be found in the AD8305 and ADL5306 data sheets.
LOG10 [IPD1/IPD2] (dB)
Figure 38. Absorbance and Absolute Power Transfer Functions for Wilson Mirror ADL5310 Combination
0.5 0.4 0.3
IPD1 = 1A
0.2
ERROR (dB)
0.1 0 -0.1 IPD1 = 10A -0.2 -0.3 -0.4 -0.5 -40 -30 -20 -10
IPD1 = 100A
04415-0-039
0
10
20
30
40
50
60
LOG10 [IPD1/IPD2] (dB)
Figure 39. Log Conformance for Wilson Mirror ADL5310 Combination, Normalized to 10 mA Channel 1 Input Current, IIN1
Rev. A | Page 16 of 20
ADL5310 EVALUATION BOARD
An evaluation board is available for the ADL5310 (Figure 40 shows the schematic). It can be configured for a wide variety of experiments. The gain of each buffer amp is factory-set to unity, providing a slope of 200 mV/dec, and the intercept is set to 300 pA. Table 4 describes the various configuration options. Table 4. Evaluation Board Configuration Options
Component P1 P2, R1, R3, R8, R9, R17, R22, R25, R30 Function Supply Interface. Provides access to the Supply Pins VNEG, COMM, and VPOS. Monitor Interface. By adding 0 resistors to R1, R3, R8, R9, R17, R22, and R25, the VRDZ, VREF, VSUM, BIN1, BIN2, OUT1, and OUT2 pin voltages can be monitored using a high impedance probe. VBIAS allows for the external bias voltages to be applied to J1 and J2. If R30 = 0 , VBIAS = VREF. Buffer Amplifier/Output Interface. The logarithmic slopes of the ADL5310 can be altered using each buffer's gain-setting resistors, R5 and R6, and R18 and R19. R7, R16, R31, R32, C19, and C20 allow for variation in the buffer loading. R20, R21, C4, C14, C15, and C16 are provided for a variety of filtering applications. Default Condition P1 = installed P2 = not installed R1 = R3 = R8 = open (size 0402) R9 = R17 = open (size 0402) R22 = R25 = R30 = open (size 0402) R5 = R19 = 0 (size 0402) R7 = R16 = 0 (size 0402) R20 = R21 = 0 (size 0402) R6 = R18 = open (size 0402) R31 = R32 = open (size 0402) C4 = C14 = open (size 0402) C19 = C20 = open (size 0402) C15 = C16 = open (size 0402) LOG1 = OUT1 = installed LOG2 = OUT2 = installed R28 = R29 = 665 k (size 0402) R2 = 0 (size 0402)
R5, R6, R7, R16, R18, R19, R20, R21, R31, R32, C4, C14, C15, C16, C19, C20
R2, R28, R29
R4, R10, R11, C2, C3, C5, C6, C8, C9 C1, C7 R12, R13, R14, R15, C10, C11, C12, C13 IREF, INPT
Intercept Adjustment. The voltage dropped across Resistors R28 and R29 determines the intercept reference current for each log amp, nominally set to 3 A using a 665 k 1% resistor. R2 can be used to adjust the output offset voltage at the LOG1 and LOG2 outputs. Supply Decoupling.
Filtering VSUM. Input Compensation. Provides essential HF compensation at the Input Pins INP1, INP2, IRF1, and IRF2.
J1, J2
Input Interface. The test board is configured to accept current through the SMA connectors labeled INP1 and INP2. Through-holes are provided to connect photodiodes in place of the INP1 and INP2 SMAs for optical interfacing. By removing R28 (R29 for INP2), a second current can be applied to the IRF1 (IRF2 for INP2) input (also SMA) for evaluating the ADL5310 in log ratio applications. SC-Style Photodiode. Provides for the direct mounting of SC-style photodiodes.
C2 = C5 = C9 = 100 pF (size 0402) C3 = C6 = C8 = 0.01 F (size 0402) R4 = R10 = R11 = 0 (size 0402) C1 = C7 = 0.01 F (size 0402) R12 = R15 = 1 k (size 0402) R13 = R14 = 2 k (size 0402) C10 = C13 = 1 nF (size 0402) C11 = C12 = 4.7 nF (size 0402) IREF = INPT = installed
J1 = J2 = open
Rev. A | Page 17 of 20
ADL5310
VRDZ R3 OPEN VBIAS R2 0 VNEG C3 0.01F R4 0 C2 100pF C1 0.01F R28 R29 665k 665k
24 23 22 21 20 19
R7 0 R32 OPEN R8 OPEN C4 OPEN R5 0 C16 OPEN R6 OPEN C20 OPEN
OUT1
3
J2 PHOTODIODE
2 1
OUT1
VREF
VNEG
COMM
COMM
VRDZ
OUT1
R20 0
R24 0
LOG1
R1 VSUM OPEN INP1
2 3 1
VSUM INP1 IRF1 IRF2 INP2 VSUM
SCL1 18 BIN1 17
LOG1 R26 0 R27 0 R21 R25 OPEN R22 OPEN R23 0 BIN1 LOG2 0 BIN2 LOG2
IRF1
ADL5310
LOG1 16 LOG2 15 BIN2 14 SCL2
13
4 5
IRF2
6
VNEG
VNEG
VPOS
VPOS
VREF
INP2 R15 1k C13 R14 2k C12 R13 2k C11 R12 1k C10 1nF R9 VREF OPEN
OUT2
C14 OPEN OPEN
R18
C15 OPEN
7
8
9
10
11
12
R19 0
OUT1 1 2 3 4 5 6 7 8 P2
04415-0-040
C5 100pF R10 0 C6 0.01F
C9 100pF R11 0 C8 0.01F
1nF 4.7nF 4.7nF
R17 OPEN
OUT2
BIN1 LOG1 LOG2 BIN2 OUT2
R16 0 R31 OPEN C19 OPEN
OUT2
3
J1 PHOTODIODE
2 1
VBIAS
AGND VPOS 1 P1 2 3 VNEG
C7 0.01F
VREF
R30 OPEN
VBIAS
Figure 40. Evaluation Board Schematic
Rev. A | Page 18 of 20
ADL5310
04415-0-041
Figure 41. Component-Side Layout
Figure 42. Component-Side Silkscreen
Rev. A | Page 19 of 20
04415-0-042
ADL5310 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 EXPOSED PAD
(BOTTOM VIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
2.25 2.10 SQ 1.95
7 6
13 12
0.25 MIN 2.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP
0.05 MAX 0.02 NOM 0.20 REF COPLANARITY 0.08
SEATING PLANE
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2
Figure 43. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm x 4 mm Body (CP-24-1) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5310ACP-R2 ADL5310ACP-REEL7 ADL5310-EVAL Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead LFCSP 24-Lead LFCSP Evaluation Board Package Outline CP-24-1 CP-24-1 Branding1 JQA JQA
1
Branding is as follows: Line 1 -- JQA Line 2 -- Lot Code Line 3 -- (Date Code) Date Code is in YYWW format
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C04415-0-9/04(A)
Rev. A | Page 20 of 20

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